# Matthew Guo

Hardware and systems engineer who owns multi-board compute and sensing platforms end to end: architecture and interface definition, schematic and layout, bring-up, cross-domain EE/firmware/mechanical debug on deployed fleets, EMI/SI root cause, and vendor-managed production. Founder of YAEDO Design House (boardmiko.com), a 5 to 10 engineer PCB design firm with its own EDA toolchain. Also builds and runs production trading systems and the risk and research infrastructure around them as Chief Investment Officer of Vosburg Capital.

Location: Mountain View, CA. Languages: English, Mandarin (native).

## Experience
- Hardware Engineer, Corvus Robotics (2025-09 to present). Sole hardware engineer across multiple platforms; owns a distributed, high-bandwidth multi-board architecture (Intel Core Ultra compute, PCIe/Thunderbolt fabric) for a space-constrained L4 autonomous drone.
- Founder and Lead Engineer, YAEDO Design House (boardmiko.com) (2026-01 to present). Founded and leads a 5 to 10 engineer PCB design and hardware services firm; owns client scoping, requirements, schedule and delivery across client engineering, non-technical stakeholders and fab and assembly partners.
- AI Research Intern, Duke University (2025-05 to 2025-07). Vision-language model research.
- Electrical Engineer, Botbuilt (2024-02 to 2025-04). Led all in-house PCB projects (10+ assemblies including IPC Class 3) and a custom NVIDIA Orin carrier that resolved sensor-bandwidth bottlenecks for on-robot AI processing.
- Mechatronics and Software Intern, Botbuilt (2023-08 to 2024-03). Modeled and solved EMI and power-distribution issues on the truss line; introduced CI for embedded firmware with hardware-in-the-loop deployment.
- Chief Investment Officer, Vosburg Capital (2026 to present). Long/short equity in hard technology. Built the firm's research, execution and risk infrastructure from scratch: two broker engines, a pre-registered research program and a parquet data lake.

## Education
- Carnegie Mellon University: B.S. Electrical and Computer Engineering (admitted) Enrollment deferred to pursue full-time hardware engineering roles.

## Capabilities
### hardware
Board and system design from architecture to production, across compute, sensing, power, RF and flex.
#### interfaces
Electrical interfaces designed, laid out, brought up or debugged on shipped or in-progress hardware.
- **high speed serial**: PCIe Gen3, Gen4 and Gen5 (topology, layout, EMI/SI root cause on deployed hardware); Thunderbolt 4 / USB4 fabric; USB 3.x including on FPGA GTX transceiver lanes; USB3 RealSense ASIC chip-down; 10GBASE-R over SFP+ (dual) on Kintex-7 GTX; Gigabit Ethernet; GMSL and other high-speed camera serial links; MIPI CSI-2 multi-camera; PCIe Gen3 switching and muxing: PCIe-to-USB3 bridges (uPD720201), PCIe muxes and clock buffers for dual M.2 slots; USB hubs (CYUSB3304), GbE switches (KSZ9893) and USB-GbE bridges (LAN7800)
- **memory**: LPDDR5X (Intel Panther Lake platform); DDR5 chip-down (RK3588S compact board); DDR3 (Kintex-7 capture board; in-house DDR3 plan/route/tune tooling); QSPI flash, eMMC, microSD, M.2 NVMe; Quad-SPI SD and octal-SPI eMMC behind a repurposed Ethernet mux for dual boot volumes
- **display and video**: eDP (NCS8803 bridge to Framework 13 panel); HDMI; multi-camera ingest into autonomy compute
- **control and fieldbus**: CAN and automotive protocols; IO-Link; I2C, SPI, UART, JTAG/SWD; FANUC and ABB robot I/O integration; 72-line LVCMOS25 parallel capture at 50 MHz DDR; Isolated IO-Link master (MAX14819) on M12 connectors; RS-422 and push-pull 24 V encoder interfaces; quadrature counting; 24 V open-collector industrial outputs at 2 A per channel; Galvanic isolation (ADuM12xx), level shifting (TXS0108), transient protection (SMAJ TVS)
- **power**: Multi-level NVDC power-delivery architecture and iMVP9.3 VR/PMIC for Intel Core Ultra; USB-C PD (20 V in) with buck conversion; Buck, boost, buck-boost (LT8705A) and LDO trees; power sequencing; Device-scale UPS modules for industrial controllers; 103 kHz series-series inductive wireless power TX/RX with LTspice models; IPC-2152 current checks and finite-difference IR-drop review; Supercapacitor power hold-up with zero-dropout changeover for clean shutdown of single-board computers; USB-C PD sink controllers (STUSB4500); ideal-diode and PPS front ends taking 8 to 60 V inputs; 42 to 60 V hot-swap inputs for stepper power; 250 W per channel motor supplies; Sub-millivolt-ripple analog supplies for load-cell front ends; low-ripple boost LED drivers (TPS61181)
- **rf and analog**: Two-channel RF receiver front end: AD8318 log detectors, PE42562 switches, QPL9547 LNA, PE43711 attenuators; Time-of-flight lidar AFE (AFBR-S50); Motor drive: 6EDL7141 gate driver, H-bridge (LM5106), AS5047P magnetic encoder; Precision environmental sensing (SHT45, BMP585); Stepper drive: TMC262 microstepping at 1/256, 2.8 A RMS per coil; Load-cell analog front ends repeatable to the ADC specification; High-power LED drive with digital colour-temperature and brightness control
- **sensors**: Multi-camera systems (MIPI CSI-2, GMSL, USB3); Lidar, optical-flow and inertial sensors; Industrial encoders, laser and optical sensors, safety and specialty sensors; Sensor power, sync/timing and bandwidth budgeting into autonomy compute
- **board types**: Chip-down SoC motherboards: Intel Panther Lake (Core Ultra 9) SoM, RK3588S compact board with onboard DDR5, NVIDIA Orin carrier, Raspberry Pi CM5 mainboard; FPGA boards: 8-layer Kintex-7 XC7K325T capture board, ~820 parts, 12.5k tracks, 3.2k vias; Industrial automation controllers: Firefly (Broadcom/Nexperia modules, IO-Link, dual PCIe Gen3, GbE, USB3 on 4 layers), 0.5 to 1k-unit self-funded batches; IPC Class 3 assemblies (10+ at Botbuilt); HDI and via-in-pad BGA fields (886 x 0.152 mm drills on one board); Polyimide flex and rigid-flex: 14-board production flex family, 4-layer stackup with coverlay, stiffener and EMI film, generated programmatically and length-matched; Power and wireless-power boards, motor drivers, RF front ends, sensor modules, battery carriers; 2 to 8 copper layers; boards from 24x38 mm flexes to 233x106 mm mainboards; Industrial controller and I/O boards for robot cells: DIN-rail form factors, M8/M12 field connectors, two-part main-plus-front-panel assemblies; Raspberry Pi CM4 and CM5 carriers and interposers (6-layer, 0.4 mm-pitch BGA, impedance controlled); Mezzanine power modules (hot-swappable stepper drivers); Single-sided assemblies designed for cost (sub-20 USD assembled boards at 50-unit volumes)
- **speeds and signal integrity**: Lanes to PCIe Gen5 / Thunderbolt 4 class rates; 10 Gbps serial; DDR5 and LPDDR5X; DDR3; Controlled-impedance stackups (rigid and flex), length and skew matching, differential-pair routing; Field-solved impedance, crosstalk and return-path review; IR-drop PI review; EMI/SI diagnosis and mitigation on deployed PCIe and Thunderbolt hardware; Flex stackup studies against a 50 ohm target across fab stack codes
- **design tools**: Altium; KiCad (daily driver; maintains a patched 10.99 fork with a guarded IPC API and routing CLI); Cadence (basic); LTspice; kicad-cli automation, scripted exports, programmatic board generation
- **validation and test**: Board and system bring-up; Oscilloscope, logic analyzer, DMM, scripted VNA; Precision rework; HALT/HASS; Hardware-in-the-loop firmware CI; Schematic-parity DRC, ERC/DRC gates, hash-replayable records of every tool run
- **manufacturing and lifecycle**: DFM/DFA review and phase-gated hardware programs with schedule, risk and trade-off tracking; Domestic and APAC design and EMS partner management; supplier, customs and production troubleshooting; native Mandarin for supplier coordination; JLC/LCSC turnkey release pipelines: readiness checks, BOM/CPL, order packages with SHA-256 manifests; BOM optimization (20 percent subsystem cost cut) and contract harness manufacturing; Fleet lifecycle: hardware versioning, IQC, provisioning and flashing, revision traceability, field serviceability; Field reliability tracking: 72.8k-hour demonstrated MTBF on a 35-unit industrial output board; Unit-cost ownership: 9.50 to 45 USD assembled boards at 20 to 50 units; 3.5k to 0.8k USD per-system I/O cost reduction; Fast-turn prototyping: 24 hours from tape-out to fabricated boards; Impedance-controlled stackups specified to the core (2116x3 resin), 1/0.5 oz and 2/1 oz copper
- **eda tooling built**: Numba A* single-ended and differential-pair routers; BGA dogbone escape; QFN fan-out; DDR3 plan/route/tune; 3W/5W spacing and impedance checks (~24k lines); Decoupling placer benchmarked on 8 open boards and 21 ICs with zero courtyard overlaps; Multi-agent packet routing with merge gates; LLM gate evaluation against human decisions; Browser workbench: board and schematic canvas, checks, worklists, LLM assistant, KiCad-fork Docker image; Client deliverable site generator: per-layer SVG with cross-probing, 3D GLB, BOM, ERC/DRC, stackup, fab zips, share links
### embedded and firmware
Firmware and embedded Linux from register level to fleet management.
- **microcontrollers**: STM32 (L4, G0) and STM8; Espressif; RP2350 embedded controller; SAMD21; GD32F303; Register-level Cortex-M bring-up
- **runtimes**: Bare-metal C/C++; RTOS; Linux device drivers; Yocto-based embedded Linux fleets with versioned provisioning, flashing and updates; Resident UART bootloaders, SEGGER RTT
- **practice**: Firmware CI with hardware-in-the-loop deployment; Python for test automation and instrument scripting; Sensor drivers over I2C/SPI/UART; CAN stacks
### software
Production backend, frontend, data and infrastructure work; about 250k lines across the trading engines alone.
- **languages**: Python (primary); TypeScript / JavaScript; C and C++; SQL; Bash
- **backend and services**: FastAPI and asyncio services with supervised tasks, crash isolation and backoff; Event-sourced domain models (immutable spec plus append-only event log); Postgres with Alembic and Prisma migrations; Redis caching; Next.js apps with Stripe payments, Resend email, Neon Postgres; Express services; Playwright browser automation exposed as a REST API
- **frontend**: React and TypeScript, Vite, Tailwind; Perspective data grids, charting, Monte Carlo payoff designers; Phone layouts, Scriptable iOS widgets, Übersicht Mac widgets; Static sites and single-file pages
- **data and ml**: Partitioned parquet lake with pyarrow (minute bars since 2016, options since 2024); LightGBM, scikit-learn, HAR-RV, PyTorch TCNs, CuPy GPU backtests, numba; EDGAR and SEC filing pipelines with documented timestamp handling; Point-in-time universes and fundamentals
- **ci deployment and ops**: Linux systemd units with WatchdogSec, timer-driven auto-deploy gated on pytest, backups and log rotation; Local CI gates: ruff, mypy --strict (explicit Any banned in core), pytest, pytest-asyncio, hypothesis, frontend typecheck and lint; pre-commit hooks; pinned lockfiles (uv, requirements.lock); Byte-identical rebuild gates for generated artifacts (research paper, flex boards); Docker images (including a KiCad fork build); Vercel deployments; GitHub Releases behind an edge proxy with password and share-link middleware; Incident runbooks, dated decision logs, spec-first development (18 specs for one engine); Firmware CI with HIL deployment
- **llm engineering**: Structured-output-only model calls; untrusted text fenced against prompt injection; every call journaled including refusals; Model fallback with cooldowns; cost caps on nightly runs; Local models (Qwen3, gpt-oss via llama.cpp) benchmarked as review gates against Opus and humans; Anthropic API quoting pipeline with pricing-engine invariant checks; MCP servers (this one)
### trading systems and risk
Production execution engines and risk controls, built and operated.
- **execution**: Two broker engines (Alpaca; Interactive Brokers via ib_async) with broker access isolated to one package; Plans with attached exits; stops and targets on filtered fair value (size-weighted micro-price); exits escalate mid, inside, touch, market; Restart-safe reconciliation against broker positions and orders; fake broker for tests; shadow mode; Per-call latency journaling; Black-Scholes P&L attribution (spread, delta/gamma, theta, vega, basis); Market data: SIP and OPRA feeds, Redis-cached bars and quotes, an OPRA options logger
- **risk controls**: Pure-function risk kernels: max loss per plan, max daily loss, max gross exposure, flatten on heartbeat loss; per-book drawdown budgets; notional caps; Resting catastrophe GTC stops at the broker; persisted fail-closed halts; kill-all with optional flatten; Operator arm/disarm lever outside the engine; off-box read-only dead-man's switch with its isolation under test; Boot-lock validators separating paper and live; explicit switch for live strategies; Nightly Flex statement reconciliation; portfolio risk and stress modules
- **research method**: Written pre-registrations before code, sha256-pinned, amended only by dated addenda; In-sample/holdout splits, placebo and shuffled nulls, Newey-West statistics; 80+ study directories; about 70 percent of studies with a verdict killed; Nightly research runner with a monthly spend cap
- **leadership and programs**: Founded and runs a 5 to 10 engineer design firm; Sole hardware owner for a multi-platform L4 drone program; Manages simulation and validation contractors and domestic and APAC EMS partners; Client scoping, binding fixed-price quoting, phase-gated delivery; Self-funded product batches of 0.5 to 1k units with go-to-market ownership

## Projects
- **Intel Panther Lake system-on-module** (2026): Solo-architected next-generation autonomous drone motherboard around the Intel Core Ultra 9 (Panther Lake) SoC; about 90 percent of the schematic captured by hand: Thunderbolt 4 / PCIe 5 topology, LPDDR5X, iMVP9.3 PMIC, multi-level NVDC power delivery. Status: Design complete through schematic.
- **Firefly automation controller** (2023-2025): Industrial controller around a Raspberry Pi Compute Module 5 with an STM32H743 co-processor: dual GbE (KSZ9893 switch, LAN7800), 2x USB 3.0 via a CYUSB3304 hub, M.2 B-key and M-key PCIe Gen3 with a PCIe mux and clock buffer, 2x HDMI 2.0, 22-pin MIPI CSI/DSI, isolated dual-channel IO-Link master (MAX14819 with MAX14931/14930 isolators) on M12-5P, USB-C sink and USB-C programming, FTDI UART, ideal-diode PPS front end taking 8 to 60 V to 5 V/5 A and 3.3 V/3 A rails. SI-aware PCIe/GbE/USB3 layout on 4 layers. Owned definition, bring-up, manufacture and go-to-market. Status: Shipped; self-funded 0.5 to 1k-unit batches (Paisley Microsystems). Firefly-5 is the current generation; Firefly-4 preceded it.
- **RK3588S compact board** (2025): Chip-down RK3588S with onboard DDR5 on the smallest RK3588 footprint in the industry; full schematic, layout and bring-up. Status: Brought up.
- **PCIe to USB 3.0 breakout for Raspberry Pi CM4** (2024): Renesas uPD720201 PCIe-to-USB3 bridge with custom EEPROM config for CM4 kernels; four USB 3.0 ports sharing a 5 Gbps PCIe link, gigabit Ethernet, 20-pin JST I/O, 24 V input, 72 mm DIN-rail profile. 4-layer 1/0.5 oz FR-4, impedance controlled on 2116x3 resin cores. Used for Intel RealSense data collection on robot elbows and end effectors. Status: Deployed on production systems (Botbuilt).
- **24 V digital output board** (2024): 16 open-collector 24 V-tolerant outputs at 2 A continuous sink for solenoids, linear motors and contactors from 3.3 V logic. Single-sided 2-layer assembly. 35 units across 5 production lines with one hardware fault in a year: 72.8k hour demonstrated MTBF. Status: In production (Botbuilt).
- **Truss-building arm controller, rev 1 and rev 2** (2024-2025): Four-axis (X, Y, theta, clamp) stepper controller around an STM32F; 1/256 microstepping at over 250 W per channel, electromagnets and break-beam sensors in a hostile-EMI cell. 42 to 60 V hot-swap input, mezzanine motor-driver modules. Rev 2 puts the Raspberry Pi CM4 on board with CM4-IO-standard I/O, Ethernet and USB. 4-layer; rev 2 impedance controlled. 45 USD per unit at 20. Status: Deployed (Botbuilt).
- **Stepper driver mezzanine (TMC262)** (2025): Single bipolar-stepper module, 44 to 60 V, 250 W sustained (2.8 A RMS per coil) with active cooling; rev 2 shrank the module and moved the motor connector on board. 4-layer 2/1 oz. 9.50 USD per unit at 30. Status: Deployed (Botbuilt).
- **Quadrature-to-digital protocol bridge** (2024): Dedicated processor counts delta and direction of four quadrature encoders at once and exposes them over I2C and UART; RS-422 adapter for industrial encoders. 2-layer, low cost, small form factor. Status: Deployed (Botbuilt).
- **IoT workplace storage unit controller** (2024): Wireless module, load-cell analog front end with a sub-0.75 mV ripple regulator at 1.3 MHz, four 12 V pass-through inputs for daisy-chaining, USB-C UART, peak-power scheme for a high-current solenoid. 4-layer. Under 16 USD assembled at 50 units. Status: Built (Botbuilt).
- **CM4 SBC interposer with power hold-up** (2024): Sits between a CM4 and its carrier; supercapacitor bank gives time for a clean shutdown on power loss via a hardware flag, zero-dropout changeover between main and backup supplies. Quad-SPI SD and octal-SPI Samsung eMMC behind a repurposed Ethernet mux, USB-C flashing without a carrier. 6-layer 1/0.5/0.5 oz, impedance controlled, 0.4 mm-pitch BGA. 26.80 USD per unit at 50. Status: Deployed (Botbuilt).
- **High-power LED light ring for computer vision** (2024): 4.5 W ring within USB 2.0 power budget, digitally controlled brightness and colour temperature. Rev 1: ATtiny1616 as I2C slave driving the LED driver; rev 2: STM32F4, TPS61181 boost driver, STUSB4500 USB-C PD sink, FT230X UART, potentiometer plus LMC555 manual mode, SWD programming. 2-layer, 88 parts, flush heatsink mounting. Deployed on every production line. Status: Deployed (Botbuilt). KiCad source on hand.
- **Truss electronics connection board** (2024): Ordered breakout for the Nucleo-based development truss platform, replacing hundreds of hand-spliced DuPont wires; 1206 parts for hand soldering, 24 hours from tape-out to fabricated boards. Status: Built (Botbuilt).
- **Input Table IO solution** (2025): Two-part DIN-rail assembly (logic main board plus front-panel connector board over a right-angle DIN 41612) reading multiple motor encoders and driving a REAJET industrial printer with push-pull 24 V encoder signals; ADuM1201 isolation, TXS0108 level shifting, ULN2002 and L293 drivers, SMAJ26A transient protection, M8 and M12 field connectors, Nucleo-F410 processor. 4-layer, 90 parts. Replaced 3.5k USD of off-the-shelf industrial I/O per system with under 0.8k USD across 5 lines. Status: Deployed (Botbuilt). KiCad source on hand.
- **NVIDIA Orin carrier** (2024): Custom carrier resolving sensor-bandwidth bottlenecks for on-robot AI processing on FANUC/ABB truss-assembly lines. Status: Deployed (Botbuilt).
- **Kintex-7 capture board** (2026): 8-layer, ~206x120 mm, XC7K325T FFG676, 72 LVCMOS25 lines at 50 MHz DDR over two Hirose FX10A-144, 2x SFP+ 10GBASE-R, USB 3.2 on GTX, DDR3, HDMI, FT4232H, USB-C PD. ~820 parts, 12.5k tracks, 3.2k vias, 0 DRC errors at last readiness check. Status: In layout (client work via YAEDO).
- **Flex extension family** (2026): 14 polyimide flexes extending a handheld device head over Samtec LSHM connectors; straight, right-angle and Z/L variants, 24x38 to 169x120 mm; generated from one 2,000-line script, byte-identical rebuilds, length-matched. Status: Several sets manufactured (client work via YAEDO).
- **Freework CM5 mainboard** (2026): Raspberry Pi CM5 mainboard for the unmodified Framework 13 chassis: inverted CM5 on a rigid bridge, RP2350B EC, NCS8803 eDP, M.2 NVMe, USB3; 8 layers, ~1,000 parts; RC2 at 0 DRC, 0 opens, 0 parity diffs. Collaborative. Status: Pre-fab audit open.
- **RF receiver front-end test board** (2026): Two-channel RF RX front end (AD8318, PE42562, QPL9547, PE43711, STM32G0B1); schematic restructured into 20 pages with netlist partition verified identical. Status: 4-layer board planned.
- **Lidar module and wireless-power pair** (2025-2026): AFBR-S50 time-of-flight module (STM32L431, SHT45, BMP585) with bare-metal C++ firmware; 103 kHz inductive charger TX/RX (LM5106, LT8705A, CAN) with LTspice models. Status: Shipped (employer).
- **CyberGear driver reverse-engineering** (2025): KiCad schematic and PCB of Xiaomi's CyberGear micro-motor driver: GD32F303, 6EDL7141, AS5047P. Status: Public on GitHub.
- **YAEDO EDA toolchain** (2026): Patched KiCad fork, routers and escape generators, DDR3 tuning, SI/PI review, benchmarked decoupling placer, workbench, deliverable site generator, hash-replayable tool records. Status: In daily use.
- **Automated quoting system** (2025-2026): Next.js, Prisma/Neon, Stripe and Anthropic API: binding, countersigned quotes from submitted specs and files, with pricing-engine invariant checks. Status: In production at boardmiko.com.
- **Alpaca trading engine** (2026): Python 3.13 / FastAPI / React / Postgres / Redis; 13 strategy modules behind one risk gate; ops console, trading terminal, widgets, OPRA logger, nightly research runner. 172k lines of Python, 1,291 backend tests. Status: Live and paper on Linux/systemd.
- **Interactive Brokers engine** (2026): Python 3.12; event-sourced plans; enforcer and reconcile loops; nightly Flex reconciliation; mypy --strict; hypothesis; 1,786 tests; 18 written specs. Status: Paper, ramping.
- **Research program** (2026): 88 study directories under pre-registration; LightGBM and HAR-RV variance forecasting, Torch TCN minute-tape pretraining, LLM memorisation controls with a written paper; EDGAR, 8-K, Form 10 and tender data. Status: Ongoing.
- **Earlier trading tooling** (2026): GPU backtester with GMM regimes (stellaron); Playwright brokerage API and dashboard (narukami, inazuma); options strategy DSL with two-way visual builder (archon); Schwab-style simulator with chaos injection (schwob). Status: Private repos.
- **Delivery-robot fleet simulator** (2026): Discrete-event simulator with replay front end and unit-economics model. Status: Complete.

## Links
- github: https://github.com/matthewguoo
- linkedin: https://www.linkedin.com/in/matthewguoo/
- boardmiko: https://www.boardmiko.com
- vosburg: https://vosburgcapital.com
- x: https://x.com/pci_yae

## Open to
- Turnkey PCB, SoC and FPGA board design through YAEDO Design House
- Senior hardware and systems roles on autonomy, robotics or compute platforms
- Conversations about trading-system and risk infrastructure
- Collaboration on EDA tooling and KiCad automation

## Contact and calls
Through the MCP server at https://matthewguo.me/mcp: `contact` sends a message, `availability` and `request_call` book a tentative call. No phone or email is published.