matthewguo.me

Matthew Guo

Hardware and systems engineer. Mountain View, CA.·English, Mandarin (native)

Hardware and systems engineer who owns multi-board compute and sensing platforms end to end: architecture and interface definition, schematic and layout, bring-up, cross-domain EE/firmware/mechanical debug on deployed fleets, EMI/SI root cause, and vendor-managed production. Founder of YAEDO Design House (boardmiko.com), a 5 to 10 engineer PCB design firm with its own EDA toolchain. Also builds and runs production trading systems and the risk and research infrastructure around them as Chief Investment Officer of Vosburg Capital.

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Experience
  1. 2025-09 → now · Mountain View, CA

    Hardware Engineer · Corvus Robotics

    • Sole hardware engineer across multiple platforms; owns a distributed, high-bandwidth multi-board architecture (Intel Core Ultra compute, PCIe/Thunderbolt fabric) for a space-constrained L4 autonomous drone.
    • Architects and integrates the perception stack: multi-camera, lidar, optical-flow and inertial sensors, with interface, power and bandwidth budgets across compute, sensor and actuator subsystems including CAN.
    • Leads bring-up and cross-domain debug of new platform builds; chases integration faults to root cause and feeds fixes back into requirements and interface specs.
    • Designs versioned, fleet-manageable hardware: IQC, provisioning and flashing, revision traceability, field serviceability.
    • Root-causes and fixes EMI/SI failures on deployed PCIe and Thunderbolt hardware, often same day; introduced risk-management gates. Manages simulation and validation contractors and domestic and APAC design and EMS partners.
  2. 2026-01 → now · Mountain View, CA

    Founder and Lead Engineer · YAEDO Design House (boardmiko.com)

    • Founded and leads a 5 to 10 engineer PCB design and hardware services firm; owns client scoping, requirements, schedule and delivery across client engineering, non-technical stakeholders and fab and assembly partners.
    • Built an automated quoting system that issues a binding, countersigned quote from submitted specs and files, backed by cost and effort models accurate enough to honor without manual review.
    • Built the firm's EDA toolchain: a patched KiCad fork with a guarded collaboration API, routers and escape generators, SI/PI review, a benchmarked decoupling placer, and client deliverable sites with fab packs.
  3. 2025-05 → 2025-07 · Durham, NC

    AI Research Intern · Duke University

    • Vision-language model research.
  4. 2024-02 → 2025-04 · Durham, NC

    Electrical Engineer · Botbuilt

    • Led all in-house PCB projects (10+ assemblies including IPC Class 3) and a custom NVIDIA Orin carrier that resolved sensor-bandwidth bottlenecks for on-robot AI processing.
    • Integrated and debugged controls, power, CAN, wiring and industrial sensing (encoders, laser and optical, safety and specialty sensors) on FANUC and ABB truss-assembly lines; fault-tolerant control architecture and device-scale UPS modules cut controls-related downtime 10x.
    • Deployed and managed a fleet of Yocto-based embedded Linux controllers with versioned provisioning, flashing and update workflows.
    • Cut subsystem BOM cost 20 percent and assembly time in half via custom modules and contract harness manufacturers; introduced phase-gating, DFM review and HALT/HASS validation.
    • Portfolio of disclosed Botbuilt boards (eleven, 2023 to 2025) is in the projects list: CM4 PCIe-to-USB3 breakout, 24 V output board, truss-arm controller and TMC262 driver modules, quadrature bridge, IoT storage controller, CM4 interposer with supercap hold-up, LED light ring, connection board, Input Table IO, Orin carrier.
  5. 2023-08 → 2024-03 · Durham, NC

    Mechatronics and Software Intern · Botbuilt

    • Modeled and solved EMI and power-distribution issues on the truss line; introduced CI for embedded firmware with hardware-in-the-loop deployment.
  6. 2026 → now · Mountain View, CA

    Chief Investment Officer · Vosburg Capital

    • Long/short equity in hard technology. Built the firm's research, execution and risk infrastructure from scratch: two broker engines, a pre-registered research program and a parquet data lake.

Carnegie Mellon University · B.S. Electrical and Computer Engineering (admitted) Enrollment deferred to pursue full-time hardware engineering roles.

Capabilities same tree the MCP walks
hardware

Board and system design from architecture to production, across compute, sensing, power, RF and flex.

interfaces

Electrical interfaces designed, laid out, brought up or debugged on shipped or in-progress hardware.

high speed serial
  • PCIe Gen3, Gen4 and Gen5 (topology, layout, EMI/SI root cause on deployed hardware)
  • Thunderbolt 4 / USB4 fabric
  • USB 3.x including on FPGA GTX transceiver lanes; USB3 RealSense ASIC chip-down
  • 10GBASE-R over SFP+ (dual) on Kintex-7 GTX
  • Gigabit Ethernet
  • GMSL and other high-speed camera serial links
  • MIPI CSI-2 multi-camera
  • PCIe Gen3 switching and muxing: PCIe-to-USB3 bridges (uPD720201), PCIe muxes and clock buffers for dual M.2 slots
  • USB hubs (CYUSB3304), GbE switches (KSZ9893) and USB-GbE bridges (LAN7800)
memory
  • LPDDR5X (Intel Panther Lake platform)
  • DDR5 chip-down (RK3588S compact board)
  • DDR3 (Kintex-7 capture board; in-house DDR3 plan/route/tune tooling)
  • QSPI flash, eMMC, microSD, M.2 NVMe
  • Quad-SPI SD and octal-SPI eMMC behind a repurposed Ethernet mux for dual boot volumes
display and video
  • eDP (NCS8803 bridge to Framework 13 panel)
  • HDMI
  • multi-camera ingest into autonomy compute
control and fieldbus
  • CAN and automotive protocols
  • IO-Link
  • I2C, SPI, UART, JTAG/SWD
  • FANUC and ABB robot I/O integration
  • 72-line LVCMOS25 parallel capture at 50 MHz DDR
  • Isolated IO-Link master (MAX14819) on M12 connectors
  • RS-422 and push-pull 24 V encoder interfaces; quadrature counting
  • 24 V open-collector industrial outputs at 2 A per channel
  • Galvanic isolation (ADuM12xx), level shifting (TXS0108), transient protection (SMAJ TVS)
power
  • Multi-level NVDC power-delivery architecture and iMVP9.3 VR/PMIC for Intel Core Ultra
  • USB-C PD (20 V in) with buck conversion
  • Buck, boost, buck-boost (LT8705A) and LDO trees; power sequencing
  • Device-scale UPS modules for industrial controllers
  • 103 kHz series-series inductive wireless power TX/RX with LTspice models
  • IPC-2152 current checks and finite-difference IR-drop review
  • Supercapacitor power hold-up with zero-dropout changeover for clean shutdown of single-board computers
  • USB-C PD sink controllers (STUSB4500); ideal-diode and PPS front ends taking 8 to 60 V inputs
  • 42 to 60 V hot-swap inputs for stepper power; 250 W per channel motor supplies
  • Sub-millivolt-ripple analog supplies for load-cell front ends; low-ripple boost LED drivers (TPS61181)
rf and analog
  • Two-channel RF receiver front end: AD8318 log detectors, PE42562 switches, QPL9547 LNA, PE43711 attenuators
  • Time-of-flight lidar AFE (AFBR-S50)
  • Motor drive: 6EDL7141 gate driver, H-bridge (LM5106), AS5047P magnetic encoder
  • Precision environmental sensing (SHT45, BMP585)
  • Stepper drive: TMC262 microstepping at 1/256, 2.8 A RMS per coil
  • Load-cell analog front ends repeatable to the ADC specification
  • High-power LED drive with digital colour-temperature and brightness control
sensors
  • Multi-camera systems (MIPI CSI-2, GMSL, USB3)
  • Lidar, optical-flow and inertial sensors
  • Industrial encoders, laser and optical sensors, safety and specialty sensors
  • Sensor power, sync/timing and bandwidth budgeting into autonomy compute
board types

Classes of board designed and taken through fabrication.

  • Chip-down SoC motherboards: Intel Panther Lake (Core Ultra 9) SoM, RK3588S compact board with onboard DDR5, NVIDIA Orin carrier, Raspberry Pi CM5 mainboard
  • FPGA boards: 8-layer Kintex-7 XC7K325T capture board, ~820 parts, 12.5k tracks, 3.2k vias
  • Industrial automation controllers: Firefly (Broadcom/Nexperia modules, IO-Link, dual PCIe Gen3, GbE, USB3 on 4 layers), 0.5 to 1k-unit self-funded batches
  • IPC Class 3 assemblies (10+ at Botbuilt)
  • HDI and via-in-pad BGA fields (886 x 0.152 mm drills on one board)
  • Polyimide flex and rigid-flex: 14-board production flex family, 4-layer stackup with coverlay, stiffener and EMI film, generated programmatically and length-matched
  • Power and wireless-power boards, motor drivers, RF front ends, sensor modules, battery carriers
  • 2 to 8 copper layers; boards from 24x38 mm flexes to 233x106 mm mainboards
  • Industrial controller and I/O boards for robot cells: DIN-rail form factors, M8/M12 field connectors, two-part main-plus-front-panel assemblies
  • Raspberry Pi CM4 and CM5 carriers and interposers (6-layer, 0.4 mm-pitch BGA, impedance controlled)
  • Mezzanine power modules (hot-swappable stepper drivers)
  • Single-sided assemblies designed for cost (sub-20 USD assembled boards at 50-unit volumes)
speeds and signal integrity

Data rates handled and the SI/PI practice behind them.

  • Lanes to PCIe Gen5 / Thunderbolt 4 class rates; 10 Gbps serial; DDR5 and LPDDR5X; DDR3
  • Controlled-impedance stackups (rigid and flex), length and skew matching, differential-pair routing
  • Field-solved impedance, crosstalk and return-path review; IR-drop PI review
  • EMI/SI diagnosis and mitigation on deployed PCIe and Thunderbolt hardware
  • Flex stackup studies against a 50 ohm target across fab stack codes
design tools
  • Altium
  • KiCad (daily driver; maintains a patched 10.99 fork with a guarded IPC API and routing CLI)
  • Cadence (basic)
  • LTspice
  • kicad-cli automation, scripted exports, programmatic board generation
validation and test
  • Board and system bring-up
  • Oscilloscope, logic analyzer, DMM, scripted VNA
  • Precision rework
  • HALT/HASS
  • Hardware-in-the-loop firmware CI
  • Schematic-parity DRC, ERC/DRC gates, hash-replayable records of every tool run
manufacturing and lifecycle
  • DFM/DFA review and phase-gated hardware programs with schedule, risk and trade-off tracking
  • Domestic and APAC design and EMS partner management; supplier, customs and production troubleshooting; native Mandarin for supplier coordination
  • JLC/LCSC turnkey release pipelines: readiness checks, BOM/CPL, order packages with SHA-256 manifests
  • BOM optimization (20 percent subsystem cost cut) and contract harness manufacturing
  • Fleet lifecycle: hardware versioning, IQC, provisioning and flashing, revision traceability, field serviceability
  • Field reliability tracking: 72.8k-hour demonstrated MTBF on a 35-unit industrial output board
  • Unit-cost ownership: 9.50 to 45 USD assembled boards at 20 to 50 units; 3.5k to 0.8k USD per-system I/O cost reduction
  • Fast-turn prototyping: 24 hours from tape-out to fabricated boards
  • Impedance-controlled stackups specified to the core (2116x3 resin), 1/0.5 oz and 2/1 oz copper
eda tooling built
  • Numba A* single-ended and differential-pair routers; BGA dogbone escape; QFN fan-out; DDR3 plan/route/tune; 3W/5W spacing and impedance checks (~24k lines)
  • Decoupling placer benchmarked on 8 open boards and 21 ICs with zero courtyard overlaps
  • Multi-agent packet routing with merge gates; LLM gate evaluation against human decisions
  • Browser workbench: board and schematic canvas, checks, worklists, LLM assistant, KiCad-fork Docker image
  • Client deliverable site generator: per-layer SVG with cross-probing, 3D GLB, BOM, ERC/DRC, stackup, fab zips, share links
embedded and firmware

Firmware and embedded Linux from register level to fleet management.

microcontrollers
  • STM32 (L4, G0) and STM8
  • Espressif
  • RP2350 embedded controller
  • SAMD21
  • GD32F303
  • Register-level Cortex-M bring-up
runtimes
  • Bare-metal C/C++
  • RTOS
  • Linux device drivers
  • Yocto-based embedded Linux fleets with versioned provisioning, flashing and updates
  • Resident UART bootloaders, SEGGER RTT
practice
  • Firmware CI with hardware-in-the-loop deployment
  • Python for test automation and instrument scripting
  • Sensor drivers over I2C/SPI/UART; CAN stacks
software

Production backend, frontend, data and infrastructure work; about 250k lines across the trading engines alone.

languages
  • Python (primary)
  • TypeScript / JavaScript
  • C and C++
  • SQL
  • Bash
backend and services
  • FastAPI and asyncio services with supervised tasks, crash isolation and backoff
  • Event-sourced domain models (immutable spec plus append-only event log)
  • Postgres with Alembic and Prisma migrations; Redis caching
  • Next.js apps with Stripe payments, Resend email, Neon Postgres
  • Express services; Playwright browser automation exposed as a REST API
frontend
  • React and TypeScript, Vite, Tailwind
  • Perspective data grids, charting, Monte Carlo payoff designers
  • Phone layouts, Scriptable iOS widgets, Übersicht Mac widgets
  • Static sites and single-file pages
data and ml
  • Partitioned parquet lake with pyarrow (minute bars since 2016, options since 2024)
  • LightGBM, scikit-learn, HAR-RV, PyTorch TCNs, CuPy GPU backtests, numba
  • EDGAR and SEC filing pipelines with documented timestamp handling
  • Point-in-time universes and fundamentals
ci deployment and ops
  • Linux systemd units with WatchdogSec, timer-driven auto-deploy gated on pytest, backups and log rotation
  • Local CI gates: ruff, mypy --strict (explicit Any banned in core), pytest, pytest-asyncio, hypothesis, frontend typecheck and lint; pre-commit hooks; pinned lockfiles (uv, requirements.lock)
  • Byte-identical rebuild gates for generated artifacts (research paper, flex boards)
  • Docker images (including a KiCad fork build); Vercel deployments; GitHub Releases behind an edge proxy with password and share-link middleware
  • Incident runbooks, dated decision logs, spec-first development (18 specs for one engine)
  • Firmware CI with HIL deployment
llm engineering
  • Structured-output-only model calls; untrusted text fenced against prompt injection; every call journaled including refusals
  • Model fallback with cooldowns; cost caps on nightly runs
  • Local models (Qwen3, gpt-oss via llama.cpp) benchmarked as review gates against Opus and humans
  • Anthropic API quoting pipeline with pricing-engine invariant checks
  • MCP servers (this one)
trading systems and risk

Production execution engines and risk controls, built and operated.

execution
  • Two broker engines (Alpaca; Interactive Brokers via ib_async) with broker access isolated to one package
  • Plans with attached exits; stops and targets on filtered fair value (size-weighted micro-price); exits escalate mid, inside, touch, market
  • Restart-safe reconciliation against broker positions and orders; fake broker for tests; shadow mode
  • Per-call latency journaling; Black-Scholes P&L attribution (spread, delta/gamma, theta, vega, basis)
  • Market data: SIP and OPRA feeds, Redis-cached bars and quotes, an OPRA options logger
risk controls
  • Pure-function risk kernels: max loss per plan, max daily loss, max gross exposure, flatten on heartbeat loss; per-book drawdown budgets; notional caps
  • Resting catastrophe GTC stops at the broker; persisted fail-closed halts; kill-all with optional flatten
  • Operator arm/disarm lever outside the engine; off-box read-only dead-man's switch with its isolation under test
  • Boot-lock validators separating paper and live; explicit switch for live strategies
  • Nightly Flex statement reconciliation; portfolio risk and stress modules
research method
  • Written pre-registrations before code, sha256-pinned, amended only by dated addenda
  • In-sample/holdout splits, placebo and shuffled nulls, Newey-West statistics
  • 80+ study directories; about 70 percent of studies with a verdict killed
  • Nightly research runner with a monthly spend cap
leadership and programs

Running teams, vendors and programs.

  • Founded and runs a 5 to 10 engineer design firm
  • Sole hardware owner for a multi-platform L4 drone program
  • Manages simulation and validation contractors and domestic and APAC EMS partners
  • Client scoping, binding fixed-price quoting, phase-gated delivery
  • Self-funded product batches of 0.5 to 1k units with go-to-market ownership
Projects
Open to